This invention relates to memory arrays and more particularly to a class of memory arrays which by virtue of their structural architecture and error correction features are capable of efficiently compensating for production defects in the active devices and interconnects of the memory array.
The prior art is replete with structural configurations used to store binary information in both volatile and nonvolatile forms. Integrated circuit nonvolatile read only memories (ROM's), to which this invention most closely relates, are well known and commonly used in applications from simple pocket calculators to complex computers having artificial intelligence.
Generally, contemporary integrated circuit ROM's are configured from individual field effect transistors (FETs) arranged in rectangular arrays on a common integrated circuit chip, such that each transistor corresponds to a memory cell of the array. Data is extracted from the individual cells or transistors by selectively addressing the cells using row and column lines enabled in response to address signals coupled to the ROM row and column decodes. One prevalent construction of the ROM cells involves the use of field effect transistors which are selectively programmed to be either depletion or enhancement mode devices through a mask-defined ion implantation procedure imposed preferably late in the fabrication cycle. Such integrated circuit ROM's normally use polycrystalline silicon for the row conductors, which correspond to the gate electrodes of the cell FETs, use diffused layers for the ground conductors within the array, and use metal layers for the bit line conductors.
With the trend toward greater ROM densities and shorter access times, more elaborate ROM architectures have evolved. An example of such appears in U.S. Pat. No. 4,602,354, assigned to the assignee of the instant application. According to the architecture of that ROM, chip density is increased through the use of NAND configured FETs, in series arrangements called stacks, which are individually accessed and isolated by bank select and column select circuits. As may be appreciated from a reading that application, the invention therein sought to optimize the line pitch through a unique arrangement of the memory architecture.
Irrespective of which technique is employed to increase the ROM density, the successful delivery of the working integrated circuit ROM chips remains vulnerable to the process constrained fabrication yields. Because the probability of random defects is relatively constant for individual cell FETs, yield effects have a great impact on high density ROMs. In an effort to increase the effective yield of high density memory chips, some manufacturers have turned to the addition of spare rows or columns. However, such approaches are not practical for low to moderate cost ROMs in that the replacement of defective rows or columns with spares must be initiated very late in the fabrication cycle, namely after the main memory array is fabricated and tested for defects. Furthermore, it is no doubt apparent that the use of this technique requires the individualized modification of each ROM, based on the location of the defects in the main memory array of such ROM, and the reprogramming of the data into the spare rows and columns.
An alternate approach to increasing chip yield involves the use of error correction coding. As depicted in FIG. 1, a ROM 1 having main memory array 2 with individually programmed FETs 3, schematically depicted at crossing points by the symbols "X", are accessed by way of row decode 4 and column decode 6 to provide output data corresponding to word bits D0-D7. Note, however, that the configuration depicted includes supplemental error correction code memory array 7, with preprogrammed error correction code bits ECC0-ECC3, which are accessed concurrent with the addressing of main memory array 2. As implemented, data word bits D0-D7 are combined with error correction bits ECC0-ECC3 in error correcting logic 8 to generate a corrected data word having bits DC0-DC7.
Unfortunately, as is understood by those having skill in the art, the addition of four error correction bits per eight bit data word can correct no more than a single bit error in each addressed word D0-D7. This limitation becomes a distinct deficiency upon recognizing that a single short circuit in a row line of main memory array will by nature of standard architecture affect all data words selected by the row bus connected to such shorted row line. Thereby, a single row line defect can affect multiple bits in multiple words, and essentially destroy the value of the error correction circuitry. Though it is possible to decouple defective row lines and substitute spare rows in place thereof, in the manner noted earlier, the circuitry for implementing such isolation and substitution operations becomes prohibitive. This is especially true when one notes the degree to which size of the ROM chip of FIG. 1 has already been increased to provide error correction code memory array 7 and error correction logic 8.
Therefore, there remains an ever-increasing need for ROM designs which are capable of overcoming manufacturing defects in the main memory array with acceptable increases in ROM chip size.